[all-commits] [llvm/llvm-project] 086670: [RISCV] Support fixed vector extract element. Use ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 086670d367869e62a3c5dffe3cd9bed04a5898c2
      https://github.com/llvm/llvm-project/commit/086670d367869e62a3c5dffe3cd9bed04a5898c2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-24 (Wed, 24 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

  Log Message:
  -----------
  [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.

I've changed to use VL=1 for slidedown and shifts to avoid extra
element processing that we don't need.

The i64 fixed vector handling on i32 isn't great if the vector type
isn't legal due to an ordering issue in type legalization. If the
vector type isn't legal, we fall back to default legalization
which will bitcast the vector to vXi32 and use two independent extracts.
Doing better will require handling several different cases by
manually inserting insert_subvector/extract_subvector to adjust the type
to a legal vector before emitting custom nodes.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97319