[all-commits] [llvm/llvm-project] fe50be: [LegalizeIntegerTypes] Further improve ExpandIntRe...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fe50be12c8b845fffd44c508ad981901d25ac5f8
      https://github.com/llvm/llvm-project/commit/fe50be12c8b845fffd44c508ad981901d25ac5f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-24 (Wed, 24 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/ARM/sadd_sat.ll
    M llvm/test/CodeGen/ARM/sadd_sat_plus.ll
    M llvm/test/CodeGen/ARM/ssub_sat.ll
    M llvm/test/CodeGen/ARM/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/ssub_sat.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll

  Log Message:
  -----------
  [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported.

Rather than converting 3 signbits to bools and comparing them,
we can do bitwise logic on the whole vector and convert the
resulting sign bit to a bool at the end.

This is still a different algorithm than what we do in LegalizeDAG
through expandSADDOSSUBO. That algorithm needs to know that the
RHS of SSUBO is > 0, but that's costly when the type is split.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97325