[all-commits] [llvm/llvm-project] 8f48dd: [X86][AMX] Lower tile copy instruction.

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f48ddd1935831979e1d7f37e47db532534b37c4
      https://github.com/llvm/llvm-project/commit/8f48ddd1935831979e1d7f37e47db532534b37c4
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2021-02-23 (Tue, 23 Feb 2021)

  Changed paths:
    M llvm/lib/Target/X86/CMakeLists.txt
    M llvm/lib/Target/X86/X86.h
    A llvm/lib/Target/X86/X86LowerTileCopy.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    A llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
    M llvm/test/CodeGen/X86/O0-pipeline.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll

  Log Message:
  -----------
  [X86][AMX] Lower tile copy instruction.

Since there is no tile copy instruction, we need to store tile
register to stack and load from stack to another tile register.
We need extra GR to hold the stride, and we need stack slot to
hold the tile data register. We would run this pass after copy
propagation, so that we don't miss copy optimization. And we
would run this pass before prolog/epilog insertion, so that we
can allocate stack slot.

Differential Revision: https://reviews.llvm.org/D97112