[all-commits] [llvm/llvm-project] 323160: [RISCV] Have sexti32 also recognize AssertZExt fro...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3231607ce95fb34adcddbdd55f8bb00b4a2a2125
      https://github.com/llvm/llvm-project/commit/3231607ce95fb34adcddbdd55f8bb00b4a2a2125
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-22 (Mon, 22 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

  Log Message:
  -----------
  [RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.

An i64 AssertZExt from a type smaller than i32 has at least 33
leading zeros which mean it has at least 33 sign bits.

Since we have a couple patterns that use two sexti32, I've
switched to a ComplexPattern so tablegen didn't have to generate
9 different permutations.

As noted in the FIXME, maybe we should just call computeNumSignBits,
but we don't have tests that benefit from that yet.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D97130