[all-commits] [llvm/llvm-project] 89440d: [ValueTracking] Improve ComputeNumSignBits for SRem.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 89440df64a5bf9981111e5980647e958f132b6a9
      https://github.com/llvm/llvm-project/commit/89440df64a5bf9981111e5980647e958f132b6a9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-22 (Mon, 22 Feb 2021)

  Changed paths:
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/test/Transforms/InstCombine/with_overflow.ll

  Log Message:
  -----------
  [ValueTracking] Improve ComputeNumSignBits for SRem.

The result will have the same sign as the dividend unless the
result is 0. The magnitude of the result will always be less
than or equal to the dividend. So the result will have at least
as many sign bits as the dividend.

Previously we would do this if the divisor was a positive constant,
but that isn't required.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97170