[all-commits] [llvm/llvm-project] 1aeb92: [RISCV] Custom isel the rest of the vector load/st...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1aeb927fedbeee328913ba085bb8860fbafaa1b1
      https://github.com/llvm/llvm-project/commit/1aeb927fedbeee328913ba085bb8860fbafaa1b1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-22 (Mon, 22 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Custom isel the rest of the vector load/store intrinsics.

A previous patch moved the index versions. This moves the rest.
I also removed the custom lowering for VLEFF since we can now
do everything directly in the isel handling.

I had to update getLMUL to handle mask registers to index the
pseudo table correctly for VLE1/VSE1.

This is good for another 15K reduction in llc size.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97097