[all-commits] [llvm/llvm-project] 60ba53: [DAG] PromoteIntRes_ADDSUBSHLSAT - use promoted IS...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 60ba5397dfbf28ffe6ec670f0cb29cf892591106
      https://github.com/llvm/llvm-project/commit/60ba5397dfbf28ffe6ec670f0cb29cf892591106
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-02-13 (Sat, 13 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
    M llvm/test/CodeGen/AMDGPU/usubsat.ll
    M llvm/test/CodeGen/ARM/usub_sat_plus.ll
    M llvm/test/CodeGen/X86/usub_sat_plus.ll
    M llvm/test/CodeGen/X86/usub_sat_vec.ll

  Log Message:
  -----------
  [DAG] PromoteIntRes_ADDSUBSHLSAT - use promoted ISD::USUBSAT directly

As discussed on D96413, as long as the promoted bits of the args are zero we can use the basic ISD::USUBSAT pattern directly, without the shifting like we do for other ops.

I think something similar should be possible for ISD::UADDSAT as well, which I'll look at later.

Also, create a ISD::USUBSAT node directly - this will be expanded back by the legalizer later on if necessary.

Differential Revision: https://reviews.llvm.org/D96622