[all-commits] [llvm/llvm-project] 7ad0c5: [DAG] Fix shift amount limit in SimplifyDemandedBi...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ad0c573bd4a68dc81886037457d47daa3d6aa24
      https://github.com/llvm/llvm-project/commit/7ad0c573bd4a68dc81886037457d47daa3d6aa24
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-02-13 (Sat, 13 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/pr49162.ll

  Log Message:
  -----------
  [DAG] Fix shift amount limit in SimplifyDemandedBits trunc(shift(x,c)) to truncated bitwidth

We lost this in D56387/rG69bc0990a9181e6eb86228276d2f59435a7fae67 - where I got the src/dst bitwidths mixed up and assumed getValidShiftAmountConstant would catch it.

Patch by @craig.topper - confirmed by @Carrot that it fixes PR49162