[all-commits] [llvm/llvm-project] 3287b6: [RISCV] Replace NoX0 SDNodeXForm with a ComplexPat...

[Kai Wang via All-commits]

  Branch: refs/heads/release/12.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 3287b6f9d552f0c542df1c7c0504aad24faf4c53
      https://github.com/llvm/llvm-project/commit/3287b6f9d552f0c542df1c7c0504aad24faf4c53
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Replace NoX0 SDNodeXForm with a ComplexPattern to do the selection of the VL operand.

I think this is a more standard way of doing this.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D95833

(cherry picked from commit e7f9a834996f40be8dc46a0b059aa850f1f4ef05)


  Commit: ef27138bb6b59ac28b28efdd1e192724ad94a1fa
      https://github.com/llvm/llvm-project/commit/ef27138bb6b59ac28b28efdd1e192724ad94a1fa
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir
    M llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
    R llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
    R llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
    R llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
    R llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll
    M llvm/test/MC/RISCV/rvv/fothers.s
    M llvm/test/MC/RISCV/rvv/invalid.s
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/store.s
    M llvm/test/MC/RISCV/rvv/vsetvl.s
    M llvm/test/MC/RISCV/rvv/zvlsseg.s

  Log Message:
  -----------
  [RISCV] Add new vector instructions in v0.10.

* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781

(cherry picked from commit c7189ba78578d029e0162720319de3c1c6fc348b)


Compare: https://github.com/llvm/llvm-project/compare/97dd9224f103...ef27138bb6b5