[all-commits] [llvm/llvm-project] ee66e4: [mlir][Vector] Introduce 'vector.load' and 'vector...

[Diego Caballero via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ee66e43a96e138cc0ed5c37897576d05fa897c27
      https://github.com/llvm/llvm-project/commit/ee66e43a96e138cc0ed5c37897576d05fa897c27
  Author: Diego Caballero <diego.caballero at intel.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/test/Conversion/AffineToStandard/lower-affine-to-vector.mlir
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][Vector] Introduce 'vector.load' and 'vector.store' ops

This patch adds the 'vector.load' and 'vector.store' ops to the Vector
dialect [1]. These operations model *contiguous* vector loads and stores
from/to memory. Their semantics are similar to the 'affine.vector_load' and
'affine.vector_store' counterparts but without the affine constraints. The
most relevant feature is that these new vector operations may perform a vector
load/store on memrefs with a non-vector element type, unlike 'std.load' and
'std.store' ops. This opens the representation to model more generic vector
load/store scenarios: unaligned vector loads/stores, perform scalar and vector
memory access on the same memref, decouple memory allocation constraints from
memory accesses, etc [1]. These operations will also facilitate the progressive
lowering of both Affine vector loads/stores and Vector transfer reads/writes
for those that read/write contiguous slices from/to memory.

In particular, this patch adds the 'vector.load' and 'vector.store' ops to the
Vector dialect, implements their lowering to the LLVM dialect, and changes the
lowering of 'affine.vector_load' and 'affine.vector_store' ops to the new vector
ops. The lowering of Vector transfer reads/writes will be implemented in the
future, probably as an independent pass. The API of 'vector.maskedload' and
'vector.maskedstore' has also been changed slightly to align it with the
transfer read/write ops and the vector new ops. This will improve reusability
among all these operations. For example, the lowering of 'vector.load',
'vector.store', 'vector.maskedload' and 'vector.maskedstore' to the LLVM dialect
is implemented with a single template conversion pattern.

[1] https://llvm.discourse.group/t/memref-type-and-data-layout/

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96185


  Commit: 656674a7c43305dbf0b4234f1086cc88f7f4e4fb
      https://github.com/llvm/llvm-project/commit/656674a7c43305dbf0b4234f1086cc88f7f4e4fb
  Author: Diego Caballero <diego.caballero at intel.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/test/Dialect/Vector/invalid.mlir

  Log Message:
  -----------
  [mlir][Vector] Align gather/scatter/expand/compress API

Align the vector gather/scatter/expand/compress API with
the vector load/store/maskedload/maskedstore API.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D96396


Compare: https://github.com/llvm/llvm-project/compare/98754e290908...656674a7c433