[all-commits] [llvm/llvm-project] c0d7a8: [AMDGPU] Allow accvgpr_read/write decode with opsel

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0d7a8bc6241a388af540798d03632075d892a9a
      https://github.com/llvm/llvm-project/commit/c0d7a8bc6241a388af540798d03632075d892a9a
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    M llvm/test/MC/Disassembler/AMDGPU/mai.txt

  Log Message:
  -----------
  [AMDGPU] Allow accvgpr_read/write decode with opsel

These two instructions are VOP3P and have op_sel_hi bits,
however do not use op_sel_hi. That is recommended to set
unused op_sel_hi bits to 1. However, we cannot decode
both representations with 1 and 0 if bits are set to
default value 1. If bits are set to be ignored with '?'
initializer then encoding defaults them to 0.

The patch is a hack to force ignored '?' bits to 1 on
encoding for these instructions.

There is still canonicalization happens on disasm print
if incoming values are non-default, so that disasm output
does not match binary input, but this is pre-existing
problem for all instructions with '?' bits.

Fixes: SWDEV-272540

Differential Revision: https://reviews.llvm.org/D96543