[all-commits] [llvm/llvm-project] 79b1b4: [Vectorizers][TTI] remove option to bypass creatio...

RotateRight via All-commits all-commits at lists.llvm.org
Fri Feb 12 05:34:46 PST 2021


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79b1b4a5815127badaf4939773b47e280f57835d
      https://github.com/llvm/llvm-project/commit/79b1b4a5815127badaf4939773b47e280f57835d
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-02-12 (Fri, 12 Feb 2021)

  Changed paths:
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    M llvm/lib/Transforms/Utils/LoopUtils.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
    M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
    M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
    M llvm/test/Transforms/LoopVectorize/debugloc.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
    M llvm/test/Transforms/LoopVectorize/flags.ll
    M llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
    M llvm/test/Transforms/LoopVectorize/if-reduction.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/loop-form.ll
    M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
    M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
    M llvm/test/Transforms/LoopVectorize/reduction.ll
    M llvm/test/Transforms/LoopVectorize/select-reduction.ll
    M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
    M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll

  Log Message:
  -----------
  [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics

The vector reduction intrinsics started life as experimental ops, so backend support
was lacking. As part of promoting them to 1st-class intrinsics, however, codegen
support was added/improved:
D58015
D90247

So I think it is safe to now remove this complication from IR.

Note that we still have an IR-level codegen expansion pass for these as discussed
in D95690. Removing that is another step in simplifying the logic. Also note that
x86 was already unconditionally forming reductions in IR, so there should be no
difference for x86.

I spot checked a couple of the tests here by running them through opt+llc and did
not see any asm diffs.

If we do find functional differences for other targets, it should be possible
to (at least temporarily) restore the shuffle IR with the ExpandReductions IR
pass.

Differential Revision: https://reviews.llvm.org/D96552




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