[all-commits] [llvm/llvm-project] 7a7836: [RISCV] Add a pattern for a scalable vector mask v...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7a7836b4d8463584eb8ee34a16096cc5ef62a8ee
      https://github.com/llvm/llvm-project/commit/7a7836b4d8463584eb8ee34a16096cc5ef62a8ee
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

  Log Message:
  -----------
  [RISCV] Add a pattern for a scalable vector mask vnot.

We can use a vnand.mm with the same register for both inputs.
This avoids materializing an alls ones constant with vmset.mm.