[all-commits] [llvm/llvm-project] 033b1b: [RISCV] Add support loads, stores, and splats of v...

Craig Topper via All-commits all-commits at lists.llvm.org
Thu Feb 11 09:17:50 PST 2021


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 033b1bd185d2ecc27bafbff6e6d95ee80f1701ac
      https://github.com/llvm/llvm-project/commit/033b1bd185d2ecc27bafbff6e6d95ee80f1701ac
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

  Log Message:
  -----------
  [RISCV] Add support loads, stores, and splats of vXi1 fixed vectors.

This refines how we determine which masks types are legal and adds
support for loads, stores, and all ones/zeros splats.

I left a fixme in store handling where I think we need to zero
extra bits if the type isn't a multiple of a byte. If I remember
right from X86 there was some case we could have a store of a
1, 2, or 4 bit mask and have a scalar zextload that then expected the
bits to be 0. Its tricky to zero the bits with RVV. We need to do
something like round VL up, zero a register, lower the VL back down,
then do a tail undisturbed move into the zero register. Another
option might be to generate a mask of 1/2/4 bits set with a VL of 8
and use that to mask off the bits.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96468




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