[all-commits] [llvm/llvm-project] 6bcc1f: [InstCombine] add tests for lshr with mul; NFC

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6bcc1fd461eeeb7946184cbfe886eead9291919c
      https://github.com/llvm/llvm-project/commit/6bcc1fd461eeeb7946184cbfe886eead9291919c
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-02-10 (Wed, 10 Feb 2021)

  Changed paths:
    M llvm/test/Transforms/InstCombine/lshr.ll

  Log Message:
  -----------
  [InstCombine] add tests for lshr with mul; NFC


  Commit: 6e2053983e0d3f69b0d9219923d7ba1eae592e12
      https://github.com/llvm/llvm-project/commit/6e2053983e0d3f69b0d9219923d7ba1eae592e12
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-02-10 (Wed, 10 Feb 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
    M llvm/test/Transforms/InstCombine/lshr.ll

  Log Message:
  -----------
  [InstCombine] fold lshr(mul X, SplatC), C2

This is a special-case multiply that replicates bits of
the source operand. We need this fold to avoid regression
if we make canonicalization to `mul` more aggressive for
shl+or patterns.

I did not see a way to make Alive generalize the bit width
condition for even-number-of-bits only, but an example of
the proof is:
  Name: i32
  Pre: isPowerOf2(C1 - 1) && log2(C1) == C2 && (C2 * 2 == width(C2))
  %m = mul nuw i32 %x, C1
  %t = lshr i32 %m, C2
  =>
  %t = and i32 %x, C1 - 2

  Name: i14
  %m = mul nuw i14 %x, 129
  %t = lshr i14 %m, 7
  =>
  %t = and i14 %x, 127

https://rise4fun.com/Alive/e52


Compare: https://github.com/llvm/llvm-project/compare/81987396ac2c...6e2053983e0d