[all-commits] [llvm/llvm-project] a5222a: [DAGCombine] Do not remove masking argument to FP1...

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a5222aa0858a42660629c410a5b669dee16a4359
      https://github.com/llvm/llvm-project/commit/a5222aa0858a42660629c410a5b669dee16a4359
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2021-02-09 (Tue, 09 Feb 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/pr48519.ll
    A llvm/test/CodeGen/PowerPC/pr49092.ll

  Log Message:
  -----------
  [DAGCombine] Do not remove masking argument to FP16_TO_FP for some targets

As of commit 284f2bffc9bc5, the DAG Combiner gets rid of the masking of the
input to this node if the mask only keeps the bottom 16 bits. This is because
the underlying library function does not use the high order bits. However, on
PowerPC's ELFv2 ABI, it is the caller that is responsible for clearing the bits
from the register. Therefore, the library implementation of __gnu_h2f_ieee will
return an incorrect result if the bits aren't cleared.

This combine is desired for ARM (and possibly other targets) so this patch adds
a query to Target Lowering to check if this zeroing needs to be kept.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=49092

Differential revision: https://reviews.llvm.org/D96283