[all-commits] [llvm/llvm-project] a719b6: [RISCV] Add initial support for converting fixed v...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a719b667a9794ec0dc820d0c5a3fd18340521ad9
      https://github.com/llvm/llvm-project/commit/a719b667a9794ec0dc820d0c5a3fd18340521ad9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-08 (Mon, 08 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

  Log Message:
  -----------
  [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

This is an alternative to D95563.

This is modeled after a similar feature for AArch64's SVE that uses
predicated scalable vector instructions.a

Rather than use predication, this patch uses an explicit VL operand.
I've limited it to always use LMUL=1 for now, but we can improve this
in the future.

This requires a bunch of new ISD opcodes to carry the VL operand.
I think we can probably lower intrinsics to these ISD opcodes to
cut down on the size of the isel table. Which is why I've added
patterns for all integer/float types and not just LMUL=1.

I'm only testing one vector width right now, but the width is
programmable via the command line.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95705