[all-commits] [llvm/llvm-project] 6c59dc: [AMDGPU] Save all lanes for reserved VGPRs

[Sebastian Neubauer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c59dc474dcc6db6daa1dad8bccc098bce4942ee
      https://github.com/llvm/llvm-project/commit/6c59dc474dcc6db6daa1dad8bccc098bce4942ee
  Author: Sebastian Neubauer <sebastian.neubauer at amd.com>
  Date:   2021-02-04 (Thu, 04 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
    M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-csr-vgpr-spill.ll
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir

  Log Message:
  -----------
  [AMDGPU] Save all lanes for reserved VGPRs

When SGPRs are spilled to VGPRs, they can overwrite any lane. We need
to preserve the value of inactive lanes in function calls, so we save
the register even if it is marked as caller saved.

Also, teach buildPrologSpill to work when no registers are free like in
CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir and update the comment on
findScratchNonCalleeSaveRegister as it is not used anymore to realign
the stack pointer since D95865.

Differential Revision: https://reviews.llvm.org/D95946