[all-commits] [llvm/llvm-project] 34da12: [DAGCombiner] Remove (sra (shl X, C), C) if X has ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34da12dd1fb327bb56f5003a727a73c78929a98d
      https://github.com/llvm/llvm-project/commit/34da12dd1fb327bb56f5003a727a73c78929a98d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-03 (Wed, 03 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/Mips/atomic.ll

  Log Message:
  -----------
  [DAGCombiner] Remove (sra (shl X, C), C) if X has more than C sign bits.

If sext_inreg is supported, we will turn this into sext_inreg. That
will then remove it if there are enough sign bits. But if sext_inreg
isn't supported, we can still remove the shift pair based on sign
bits.

Split from D95890.