[all-commits] [llvm/llvm-project] c7189b: [RISCV] Add new vector instructions in v0.10.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c7189ba78578d029e0162720319de3c1c6fc348b
      https://github.com/llvm/llvm-project/commit/c7189ba78578d029e0162720319de3c1c6fc348b
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-03 (Wed, 03 Feb 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir
    M llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
    R llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
    R llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
    R llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
    R llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll
    M llvm/test/MC/RISCV/rvv/fothers.s
    M llvm/test/MC/RISCV/rvv/invalid.s
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/store.s
    M llvm/test/MC/RISCV/rvv/vsetvl.s
    M llvm/test/MC/RISCV/rvv/zvlsseg.s

  Log Message:
  -----------
  [RISCV] Add new vector instructions in v0.10.

* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781