[all-commits] [llvm/llvm-project] af2cbe: AMDGPU: Fix adding extra operands for i128 asm con...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af2cbe8effcade9913c0f2cff295f664f185df54
      https://github.com/llvm/llvm-project/commit/af2cbe8effcade9913c0f2cff295f664f185df54
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-02-02 (Tue, 02 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    A llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll

  Log Message:
  -----------
  AMDGPU: Fix adding extra operands for i128 asm constraints

We don't register i128 as a legal type with addRegisterClass, but it
appears in the list of legal register types. This inconsistency
resulted in the asm constraint lowering trying to use 2 128-bit
registers for these operands. This would leave behind a dead def that
would waste registers.

Regresses GlobalISel tests for i128 load/store, but these aren't very
important right now. Ideally these would not depend on the list of
register types.