[all-commits] [llvm/llvm-project] 1097ee: [RISCV] Optimize (srl (and X, 0xffff), C) -> (srli...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1097ee61bf3ef4f36a7e92b4d8781a5c069c93de
      https://github.com/llvm/llvm-project/commit/1097ee61bf3ef4f36a7e92b4d8781a5c069c93de
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-01 (Mon, 01 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/alu16.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

  Log Message:
  -----------
  [RISCV] Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).

Rather than materializing the 0xffff immediate for the AND, use
a shift left to remove the upper bits and then shift in zeros
from the right.

This pattern occurs when type legalizing an i16 right shift.

I've implemented this with custom selection code for a number of
reasons. I've limited this to the AND having a single use. We need
to compensate for SimplifyDemandedBits altering the AND mask. I'm
using *W opcodes on RV64. We may want to generlize this in the
future. For all these reason it seemed easiest to do it this way.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95774