[all-commits] [llvm/llvm-project] 8f14a0: AMDGPU: Add missing consts

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f14a08863bf295cdc660f24948ef810731b812d
      https://github.com/llvm/llvm-project/commit/8f14a08863bf295cdc660f24948ef810731b812d
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-01-31 (Sun, 31 Jan 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  Log Message:
  -----------
  AMDGPU: Add missing consts


  Commit: 1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3
      https://github.com/llvm/llvm-project/commit/1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-01-31 (Sun, 31 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocBase.cpp
    A llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir

  Log Message:
  -----------
  RegAlloc: Fix assert if all registers in class reserved

With a context instruction, this would produce a context
error. However, it would continue on and do an out of bounds access of
the empty allocation order array.


Compare: https://github.com/llvm/llvm-project/compare/7de711ecca99...1801e2aa2494