[all-commits] [llvm/llvm-project] a5d9e0: [X86] Fix tile config register spill issue.

[Pengfei Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a5d9e0c79befb6856ae78a3c5f515287ad89a40f
      https://github.com/llvm/llvm-project/commit/a5d9e0c79befb6856ae78a3c5f515287ad89a40f
  Author: Wang, Pengfei <pengfei.wang at intel.com>
  Date:   2021-01-30 (Sat, 30 Jan 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86InstrAMX.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86PreTileConfig.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/Target/X86/X86TileConfig.cpp
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    M llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
    A llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

  Log Message:
  -----------
  [X86] Fix tile config register spill issue.

This is an optimized approach for D94155.

Previous code build the model that tile config register is the user of
each AMX instruction. There is a problem for the tile config register
spill. When across function, the ldtilecfg instruction may be inserted
on each AMX instruction which use tile config register. This cause all
tile data register clobber.

To fix this issue, we remove the model of tile config register. Instead,
we analyze the AMX instructions between one call to another. We will
insert ldtilecfg after the first call if we find any AMX instructions.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D95136