[all-commits] [llvm/llvm-project] e08b67: [NFC][RISCV] Remove redundant pseudo instructions ...

Kai Wang via All-commits all-commits at lists.llvm.org
Fri Jan 29 15:21:09 PST 2021


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e08b67f3a8ada62dcf84d41929c208adc656ba92
      https://github.com/llvm/llvm-project/commit/e08b67f3a8ada62dcf84d41929c208adc656ba92
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-30 (Sat, 30 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [NFC][RISCV] Remove redundant pseudo instructions for vector load/store.

Not all combinations of SEW and LMUL we need to support. For example, we
only need to support [M1, M2, M4, M8] for SEW = 64. There is no need to
define pseudos for PseudoVLSE64MF8, PseudoVLSE64MF4, and PseudoVLSE64MF2.

Differential Revision: https://reviews.llvm.org/D95667


  Commit: 282aca10aeb03bdaef0a8d4f3faa4c2ff236e527
      https://github.com/llvm/llvm-project/commit/282aca10aeb03bdaef0a8d4f3faa4c2ff236e527
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-30 (Sat, 30 Jan 2021)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] Update the version number to v0.10 for vector.

v0.10 is tagged in V specification. Update the version to v0.10.

Differential Revision: https://reviews.llvm.org/D95680


Compare: https://github.com/llvm/llvm-project/compare/9dbe736cbd2c...282aca10aeb0


More information about the All-commits mailing list