[all-commits] [llvm/llvm-project] b9ed8e: [ARM][RegisterScavenging] Don't consider LR liveou...

[tmatheson-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b9ed8ebe0e2ffa803b0bda60f9bbc9bb26f95000
      https://github.com/llvm/llvm-project/commit/b9ed8ebe0e2ffa803b0bda60f9bbc9bb26f95000
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2021-01-28 (Thu, 28 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/LiveRegUnits.cpp
    A llvm/test/CodeGen/AArch64/scavenge-lr.mir
    M llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll

  Log Message:
  -----------
  [ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded

https://bugs.llvm.org/show_bug.cgi?id=48232

When PrologEpilogInserter writes callee-saved registers to the stack, LR is not reloaded but is instead loaded directly into PC.
This was not taken into account when determining if each callee-saved register was liveout for the block.
When frame elimination inserts virtual registers, and the register scavenger tries to scavenge LR, it considers it liveout and tries to spill again.
However there is no emergency spill slot to use, and it fails with an error:

    fatal error: error in backend: Error while trying to spill LR from class GPR: Cannot scavenge register without an emergency spill slot!

This patch pervents any callee-saved registers which are not reloaded (including LR) from being marked liveout.
They are therefore available to scavenge without requiring an extra spill.