[all-commits] [llvm/llvm-project] d91ee2: [AMDGPU] Do not reassign spilled registers

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d91ee2f782ebeec7ae0b5f8ca879c4f10dccb29f
      https://github.com/llvm/llvm-project/commit/d91ee2f782ebeec7ae0b5f8ca879c4f10dccb29f
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-01-27 (Wed, 27 Jan 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
    M llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
    A llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
    A llvm/test/CodeGen/AMDGPU/regbank-reassign-split.mir

  Log Message:
  -----------
  [AMDGPU] Do not reassign spilled registers

We cannot call LRM::unassign() if LRM::assign() was never called
before, these are symmetrical calls. There are two ways of
assigning a physical register to virtual, via LRM::assign() and
via VRM::assignVirt2Phys(). LRM::assign() will call the VRM to
assign the register and then update LiveIntervalUnion. Inline
spiller calls VRM directly and thus LiveIntervalUnion never gets
updated. A call to LRM::unassign() then asserts about inconsistent
liveness.

We have to note that not all callers of the InlineSpiller even
have LRM to pass, RegAllocPBQP does not have it, so we cannot
always pass LRM into the spiller.

The only way to get into that spiller LRE_DidCloneVirtReg() call
is from LiveRangeEdit::eliminateDeadDefs if we split an LI.

This patch refuses to reassign a LiveInterval created by a split
to workaround the problem. In fact we cannot reassign a spill
anyway as all registers of the needed class are occupied and we
are spilling.

Fixes: SWDEV-267996

Differential Revision: https://reviews.llvm.org/D95489