[all-commits] [llvm/llvm-project] 3d25fd: [AArch64][GlobalISel] Allow vector store legalizat...

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d25fdc5c21f174d38ac78dd01ccaf6eec655bc0
      https://github.com/llvm/llvm-project/commit/3d25fdc5c21f174d38ac78dd01ccaf6eec655bc0
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2021-01-27 (Wed, 27 Jan 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Allow vector store legalization into 128-bit-wide types

We are allowed to store 128-bit-wide values using the q registers on AArch64.

GlobalISel was clamping the number of elements in vector stores into 64 bits
instead.

This results in some poor codegen like below:

https://godbolt.org/z/E56dq8

```
; SDAG uses a stp + q registers in both cases here.
define void @float(<16 x float> %val, <16 x float>* %ptr) {
 store <16 x float> %val, <16 x float>* %ptr
 ret void
}

define void @double(<8 x double> %val, <8 x double>* %ptr) {
 store <8 x double> %val, <8 x double>* %ptr
 ret void
}
```

This adds similar legalization for vector stores with s8 and s16 elements.

Differential Revision: https://reviews.llvm.org/D95107