[all-commits] [llvm/llvm-project] 04570e: [RISCV] Group the legal vector types into lists we...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 04570e98c85f7cd35577f8193ac04ecd3bc38fea
      https://github.com/llvm/llvm-project/commit/04570e98c85f7cd35577f8193ac04ecd3bc38fea
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-27 (Wed, 27 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor

Remove the RISCVVMVTs namespace because I don't think it provides
a lot of value. If we change the mappings we'd likely have to add
or remove things from the list anyway.

Add a wrapper around addRegisterClass that can determine the
register class from the fixed size of the type.

Reviewed By: frasercrmck, rogfer01

Differential Revision: https://reviews.llvm.org/D95491