[all-commits] [llvm/llvm-project] 1d6df1: [mlir] sret and byval now require a type argument ...
Eric Schweitz via All-commits
all-commits at lists.llvm.org
Tue Jan 26 10:52:38 PST 2021
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 1d6df1fcf0a754adff8b66f3445d7d5ab130434e
https://github.com/llvm/llvm-project/commit/1d6df1fcf0a754adff8b66f3445d7d5ab130434e
Author: Eric Schweitz <eschweitz at nvidia.com>
Date: 2021-01-26 (Tue, 26 Jan 2021)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/llvmir.mlir
Log Message:
-----------
[mlir] sret and byval now require a type argument when constructed.
Fixes the LLVM code gen bugs and adds the missing tests.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D95378
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