[all-commits] [llvm/llvm-project] bfc60a: [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for di...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bfc60acd98036925f8314691c6d13ef921f8188e
      https://github.com/llvm/llvm-project/commit/bfc60acd98036925f8314691c6d13ef921f8188e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-26 (Tue, 26 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll

  Log Message:
  -----------
  [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.

Move the Suffix string into the VTypeInfo class so we don't need a helper class to get to it.

Adjust pseudo naming scheme for FPRs to put F16/F32/F64 in
place of F in the pseudo instruction name rather than as a suffix.
This avoids special cases like VFMERGE from the original patch.

Differential Revision: https://reviews.llvm.org/D95404