[all-commits] [llvm/llvm-project] e72b22: [RISCV] Define different pseudo instructions for d...

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e72b22a40b09f533cbcf2517800692ce0fddff7e
      https://github.com/llvm/llvm-project/commit/e72b22a40b09f533cbcf2517800692ce0fddff7e
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-26 (Tue, 26 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll

  Log Message:
  -----------
  [RISCV] Define different pseudo instructions for different FPR.

When spilling, the spill size will depend on the size of register class.
For .vf vector instructions, it may spill the floating point scalar
argument. In order to use the correct load/store instructions for
spilling, we need to provide the correct floating point register class
for the .vf vector pseudo instructions.

In this commit, we define the .vf pseudo instructions as three
different kinds of pseudo instructions for half/float/double. For
example, PseudoVFADD_M1 will become as PseudoVFADD_F16_M1,
PseudoVFADD_F32_M1, and PseudoVFADD_F64_M1.

Differential Revision: https://reviews.llvm.org/D95234