[all-commits] [llvm/llvm-project] ea87cf: [TargetLowering][RISCV] Don't transform (seteq/ne ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ea87cf2acd82e435e485c6e1884b54ba7427a54d
      https://github.com/llvm/llvm-project/commit/ea87cf2acd82e435e485c6e1884b54ba7427a54d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-25 (Mon, 25 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

  Log Message:
  -----------
  [TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper

RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we
can use addiw rd, rs1, x0 for sext_inreg. We already understood this
when type legalizing i32 seteq/ne on rv64. But this transform in
SimplifySetCC would sometimes undo it.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95289