[all-commits] [llvm/llvm-project] 15141c: [RISCV] Add RVV insertelt/extractelt scalable-vect...

[Fraser Cormack via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 15141cd115e068104cc61f32ada05bebf5ef03a5
      https://github.com/llvm/llvm-project/commit/15141cd115e068104cc61f32ada05bebf5ef03a5
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-01-25 (Mon, 25 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

  Log Message:
  -----------
  [RISCV] Add RVV insertelt/extractelt scalable-vector patterns

Original patch by @rogfer01.

This patch adds support for insertelt and extractelt operations on
scalable vectors.

Special care must be taken on RV32 when dealing with i64 vectors as
there are no straightforward ways to insert a 64-bit element without a
register of that size. To that end, both are custom-lowered to different
sequences.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94615