[all-commits] [llvm/llvm-project] 239cfb: [RISCV] Custom type legalize i8/i16 UDIV/UREM/SDIV...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 239cfbccb0509da1a08d9e746706013b732e646b
      https://github.com/llvm/llvm-project/commit/239cfbccb0509da1a08d9e746706013b732e646b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-25 (Mon, 25 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

  Log Message:
  -----------
  [RISCV] Custom type legalize i8/i16 UDIV/UREM/SDIV on RV64 so we can use divuw/remuw/divw.

This makes our i8/i16 codegen more similar to the i32 codegen.

I've also added computeKnownBits support for DIVUW/REMUW so
that we can remove zero extending ANDs from the output. Without
this we end up turning DIVUW/REMUW back into DIVU/REMU via some
isel patterns.

Reviewed By: frasercrmck, luismarques

Differential Revision: https://reviews.llvm.org/D95322