[all-commits] [llvm/llvm-project] c50457: [RISCV] Make the code in MatchSLLIUW ignore the lo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c50457f3e4209b0cd0d4a6baa881bac30a9d3016
      https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-24 (Sun, 24 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.

This avoids being dependent on SimplifyDemandedBits having cleared
those bits.

It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.