[all-commits] [llvm/llvm-project] 5a73da: [RISCV] Add test cases for SRO/SLO with shift amou...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5a73daf907873a8757213932f814361a59f02da5
      https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC

The sro/slo instructions ignore extra bits in the shift amount,
so we can ignore the mask just like we do for sll, srl, and sra.


  Commit: 998057ec06ae7e0fb1e0be0f2702df4d6338a128
      https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.


Compare: https://github.com/llvm/llvm-project/compare/d2927f786e87...998057ec06ae