[all-commits] [llvm/llvm-project] d2927f: [RISCV] Add isel patterns to remove (and X, 31) fr...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2927f786e877410d90c1e6f0e0c7d99524529c5
      https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.

We try to do this during DAG combine with SimplifyDemandedBits,
but it fails if there are multiple nodes using the AND. For
example, multiple shifts using the same shift amount.