[all-commits] [llvm/llvm-project] 97e33f: [RISCV] Implement vloxseg/vluxseg intrinsics.

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 97e33feb08aa9c042408862e555423f037753e12
      https://github.com/llvm/llvm-project/commit/97e33feb08aa9c042408862e555423f037753e12
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Implement vloxseg/vluxseg intrinsics.

Define vloxseg/vluxseg intrinsics and pseudo instructions.
Lower vloxseg/vluxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94903


  Commit: a41cb92eb81b3c1446b563f1483fbe71feecc1ee
      https://github.com/llvm/llvm-project/commit/a41cb92eb81b3c1446b563f1483fbe71feecc1ee
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Add RV32 test cases for vluxseg.

Differential Revision: https://reviews.llvm.org/D95193


  Commit: b23fe6ff6ff736a5d319598bc818defc09968200
      https://github.com/llvm/llvm-project/commit/b23fe6ff6ff736a5d319598bc818defc09968200
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Add RV64 test cases for vluxseg.

Differential Revision: https://reviews.llvm.org/D95190


  Commit: 9e5beadf1805a5906c2ea0d04eb615ce5f92508b
      https://github.com/llvm/llvm-project/commit/9e5beadf1805a5906c2ea0d04eb615ce5f92508b
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Add RV32 test cases for vloxseg.

Differential Revision: https://reviews.llvm.org/D95191


  Commit: c28bbd97a15d1942ba63998e7ba8609cc87b38ae
      https://github.com/llvm/llvm-project/commit/c28bbd97a15d1942ba63998e7ba8609cc87b38ae
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Add RV64 test cases for vloxseg.

Differential Revision: https://reviews.llvm.org/D95192


  Commit: 66a49aef690cb2980152d3cfa867e797bbda54be
      https://github.com/llvm/llvm-project/commit/66a49aef690cb2980152d3cfa867e797bbda54be
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Implement vsoxseg/vsuxseg intrinsics.

Define vsoxseg/vsuxseg intrinsics and pseudo instructions.
Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94940


  Commit: a28755003782b97062b19867cfab201816d8dd5f
      https://github.com/llvm/llvm-project/commit/a28755003782b97062b19867cfab201816d8dd5f
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Add RV32 test cases for vsuxseg.

Differential Revision: https://reviews.llvm.org/D95196


  Commit: 438e118c29a0610dbd44569aff54b5d87684b333
      https://github.com/llvm/llvm-project/commit/438e118c29a0610dbd44569aff54b5d87684b333
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Add RV64 test cases for vsuxseg.

Differential Revision: https://reviews.llvm.org/D95197


  Commit: 408ed11c85d9e70131b77a9125775ace3643663c
      https://github.com/llvm/llvm-project/commit/408ed11c85d9e70131b77a9125775ace3643663c
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Add RV32 test cases for vsoxseg.

Differential Revision: https://reviews.llvm.org/D95194


  Commit: dc94cecac036b151cb4cababf5b0d986df39ac23
      https://github.com/llvm/llvm-project/commit/dc94cecac036b151cb4cababf5b0d986df39ac23
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-23 (Sat, 23 Jan 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Add RV64 test cases for vsoxseg.

Differential Revision: https://reviews.llvm.org/D95195


Compare: https://github.com/llvm/llvm-project/compare/ef51eed37b7e...dc94cecac036