[all-commits] [llvm/llvm-project] 6aced6: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip s...

Fri Jan 22 12:56:07 PST 2021

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6aced6bf396b78b0021a224bf210ffc3598c3047
      https://github.com/llvm/llvm-project/commit/6aced6bf396b78b0021a224bf210ffc3598c3047
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/MC/RISCV/rv32zbb-invalid.s
    M llvm/test/MC/RISCV/rv32zbb-valid.s
    M llvm/test/MC/RISCV/rv64zbb-invalid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s

  Log Message:
  -----------
  [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec.

This is the first of multiple patches to bring our 0.92
implementation up to 0.93.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94568

  Commit: b2f859500f196f98a73d531c2ec847b7f23875af
      https://github.com/llvm/llvm-project/commit/b2f859500f196f98a73d531c2ec847b7f23875af
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/MC/RISCV/rv64zbb-invalid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s
    R llvm/test/MC/RISCV/rv64zbc-invalid.s
    R llvm/test/MC/RISCV/rv64zbc-valid.s

  Log Message:
  -----------
  [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94577

  Commit: d985c7321f0b9cbaf8f8423a7faa645bb5966fc8
      https://github.com/llvm/llvm-project/commit/d985c7321f0b9cbaf8f8423a7faa645bb5966fc8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/MC/RISCV/rv32zbb-valid.s

  Log Message:
  -----------
  [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94580

  Commit: b825278364d9551ec3e8eb9f776f722238c9b3d8
      https://github.com/llvm/llvm-project/commit/b825278364d9551ec3e8eb9f776f722238c9b3d8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/MC/RISCV/rv64zbb-invalid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s

  Log Message:
  -----------
  [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94582

  Commit: 4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024
      https://github.com/llvm/llvm-project/commit/4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/CodeGen/RISCV/rv64Zba.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    A llvm/test/MC/RISCV/rv64zba-invalid.s
    A llvm/test/MC/RISCV/rv64zba-valid.s
    M llvm/test/MC/RISCV/rv64zbb-invalid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s

  Log Message:
  -----------
  [RISCV] Add Zba feature and move add.uw and slli.uw to it.

Still need to add SH*ADD instructions.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94617

  Commit: 83a93ae63b1c8cc515a08c7fc4b78813e448c874
      https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    A llvm/test/MC/RISCV/rv32zba-invalid.s
    A llvm/test/MC/RISCV/rv32zba-valid.s
    M llvm/test/MC/RISCV/rv64zba-invalid.s
    M llvm/test/MC/RISCV/rv64zba-valid.s

  Log Message:
  -----------
  [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94637

  Commit: 1355458ef665b3044e3dfb57acf0c2e7439560fe
      https://github.com/llvm/llvm-project/commit/1355458ef665b3044e3dfb57acf0c2e7439560fe
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll
    M llvm/test/MC/RISCV/rv32zbb-invalid.s
    M llvm/test/MC/RISCV/rv32zbb-valid.s
    M llvm/test/MC/RISCV/rv32zbp-invalid.s
    M llvm/test/MC/RISCV/rv32zbp-valid.s
    M llvm/test/MC/RISCV/rv64zbb-invalid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s
    M llvm/test/MC/RISCV/rv64zbp-invalid.s
    M llvm/test/MC/RISCV/rv64zbp-valid.s

  Log Message:
  -----------
  [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec.

It's not really clear in the spec that these are in Zbp now, but
that's what I've gather from previous commits to the spec. I've
file an issue to get it documented properly.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94652

  Commit: efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2
      https://github.com/llvm/llvm-project/commit/efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbs.ll
    M llvm/test/CodeGen/RISCV/rv32Zbt.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbs.ll
    M llvm/test/MC/RISCV/rv32zbe-invalid.s
    M llvm/test/MC/RISCV/rv32zbe-valid.s
    M llvm/test/MC/RISCV/rv32zbs-invalid.s
    M llvm/test/MC/RISCV/rv32zbs-valid.s
    M llvm/test/MC/RISCV/rv64zbe-invalid.s
    M llvm/test/MC/RISCV/rv64zbe-valid.s
    M llvm/test/MC/RISCV/rv64zbs-invalid.s
    M llvm/test/MC/RISCV/rv64zbs-valid.s

  Log Message:
  -----------
  [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.

Also renamed Zbe instructions to resolve name conflict even though
that change is in the 0.94 draft.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94653

  Commit: 9d499e037e6bc3365e6ad1423a388dc7a37627b0
      https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zba.ll

  Log Message:
  -----------
  [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
  uint_xlen_t rs1u = (uint32_t)rs1;
  return rs1u + rs2;
}

The 0.92 spec had the usages of rs1 and rs2 swapped.

Reviewed By: frasercrmck, asb

Differential Revision: https://reviews.llvm.org/D95090

  Commit: 5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc
      https://github.com/llvm/llvm-project/commit/5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zba.ll
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll
    M llvm/test/MC/RISCV/rv64b-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack.

This didn't make it into the published 0.93 spec, but it was the
intention.

But it is in the tex source as of this commit
https://github.com/riscv/riscv-bitmanip/commit/d172f029c074d47026a0c0d0f12d8b475c86a472

This means zext.w now requires Zba. Not sure if we should still use
pack if Zbp is enabled and Zba isn't. I'll leave that for the future
when pack is closer to being final.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94736

  Commit: 83c92fdeda6be9a42739fa699926d41ce8a001fb
      https://github.com/llvm/llvm-project/commit/83c92fdeda6be9a42739fa699926d41ce8a001fb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll
    M llvm/test/MC/RISCV/rv32zbbp-invalid.s
    M llvm/test/MC/RISCV/rv32zbbp-valid.s
    M llvm/test/MC/RISCV/rv32zbp-invalid.s
    M llvm/test/MC/RISCV/rv32zbp-valid.s
    M llvm/test/MC/RISCV/rv64zbbp-valid.s
    M llvm/test/MC/RISCV/rv64zbp-valid.s

  Log Message:
  -----------
  [RISCV] Move pack instructions to Zbp extension only.

Zext.h will need to come back to Zbb, but that only uses specific
encodings of pack.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94742

  Commit: 3c94cee63b401ca12457395bb1f4d70e161f9ec4
      https://github.com/llvm/llvm-project/commit/3c94cee63b401ca12457395bb1f4d70e161f9ec4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/MC/RISCV/rv32b-aliases-valid.s
    M llvm/test/MC/RISCV/rv32zbb-valid.s
    M llvm/test/MC/RISCV/rv32zbp-valid.s
    M llvm/test/MC/RISCV/rv64b-aliases-valid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s
    M llvm/test/MC/RISCV/rv64zbp-valid.s

  Log Message:
  -----------
  [RISCV] Add zext.h instruction to Zbb.

zext.h uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.

I've added two new instructions with these specific encodings with
predicates that enable them when either Zbb or Zbp is enabled.

The pack spelling will only be accepted with Zbp. The disassembler
will use the zext.h instruction when either feature is enabled.

Using the pack spelling will print as pack when llvm-mc is
emitting text. We could fix this with some custom code in
processInstruction if this is important, but I'm not sure it is.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94818

  Commit: 4d5aa760a7d78b601fcfbda4d6196091a9188ea6
      https://github.com/llvm/llvm-project/commit/4d5aa760a7d78b601fcfbda4d6196091a9188ea6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/MC/RISCV/rv32b-aliases-valid.s
    M llvm/test/MC/RISCV/rv32zbb-valid.s
    M llvm/test/MC/RISCV/rv32zbp-valid.s
    M llvm/test/MC/RISCV/rv64b-aliases-valid.s
    M llvm/test/MC/RISCV/rv64zbb-valid.s
    M llvm/test/MC/RISCV/rv64zbp-valid.s

  Log Message:
  -----------
  [RISCV] Add support for rev8 and orc.b to Zbb.

These instructions use a portion of the encodings for grevi and
gorci. The full encodings are only supported with Zbp. Note,
rev8 has a different encoding between rv32 and rv64.

Zbb is closer to being finalized that Zbp which has motivated
some decisions in this patch.

I'm treating rev8 and orc.b as separate instructions when
either Zbb or Zbp is enabled. This allows us to print to suggest
that either feature needs to be enabled to support these mnemonics.
I had tried to put HasStdExtZbbAndNotZbp on the Zbb instructions,
but that caused a diagnostic that said Zbp is required if neither
feature is enabled. We should really mention Zbb since its closer
to final.

This does require extra isel patterns for the different cases so
that bswap will always print as rev8 in assembly listing since
we can't use an InstAlias.

llvm-objdump disassembling should always pick the rev8 or orc.b
instructions. llvm-mc parsing and printing text will not convert
the grevi/gorci spellings to rev8/gorc.b. We could probably fix
this with a special case in processInstruction in the assembly
parser if it its important.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94944

  Commit: f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
      https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/MC/RISCV/rv32zbp-invalid.s
    M llvm/test/MC/RISCV/rv32zbp-valid.s
    M llvm/test/MC/RISCV/rv64zbp-invalid.s
    M llvm/test/MC/RISCV/rv64zbp-valid.s

  Log Message:
  -----------
  [RISCV] Add xperm.* instructions to Zbp extension.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94999

  Commit: 20f2e32d2c545e6e23dc5c69c42caac7a4bca0fc
      https://github.com/llvm/llvm-project/commit/20f2e32d2c545e6e23dc5c69c42caac7a4bca0fc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td

  Log Message:
  -----------
  [RISCV] Update B extension version to 0.93.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D95002

Compare: https://github.com/llvm/llvm-project/compare/9d2796210f71...20f2e32d2c54