[all-commits] [llvm/llvm-project] 16d4bb: [mlir][Linalg] Introduce linalg.pad_tensor op.
Han-Chung Wang via All-commits
all-commits at lists.llvm.org
Thu Jan 21 22:26:01 PST 2021
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 16d4bbef30a9e625e04653047759d5636f9e58a5
https://github.com/llvm/llvm-project/commit/16d4bbef30a9e625e04653047759d5636f9e58a5
Author: Hanhan Wang <hanchung at google.com>
Date: 2021-01-21 (Thu, 21 Jan 2021)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/roundtrip.mlir
Log Message:
-----------
[mlir][Linalg] Introduce linalg.pad_tensor op.
`linalg.pad_tensor` is an operation that pads the `source` tensor
with given `low` and `high` padding config.
Example 1:
```mlir
%pad_value = ... : f32
%1 = linalg.pad_tensor %0 low[1, 2] high[2, 3] {
^bb0(%arg0 : index, %arg1 : index):
linalg.yield %pad_value : f32
} : tensor<?x?xf32> to tensor<?x?xf32>
```
Example 2:
```mlir
%pad_value = ... : f32
%1 = linalg.pad_tensor %arg0 low[2, %arg1, 3, 3] high[3, 3, %arg1, 2] {
^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index):
linalg.yield %pad_value : f32
} : tensor<1x2x2x?xf32> to tensor<6x?x?x?xf32>
```
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D93704
Commit: 2cb130f7661176f2c2eaa7554f2a55863cfc0ed3
https://github.com/llvm/llvm-project/commit/2cb130f7661176f2c2eaa7554f2a55863cfc0ed3
Author: Hanhan Wang <hanchung at google.com>
Date: 2021-01-21 (Thu, 21 Jan 2021)
Changed paths:
M mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
Log Message:
-----------
[mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V
- Extend spirv::ConstantOp::getZero/One to handle float, vector of int, and vector of float.
- Refactor ZeroExtendI1Pattern to use getZero/One methods.
- Add one more test for lowering std.zexti which extends vector<4xi1> to vector<4xi64>.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D95120
Compare: https://github.com/llvm/llvm-project/compare/f374138058b6...2cb130f76611
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