[all-commits] [llvm/llvm-project] 5d3542: [RISCV] Correct DWARF number for vector registers.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d354220d44f11c70f36d5a357ec2a2208a6ab92
      https://github.com/llvm/llvm-project/commit/5d354220d44f11c70f36d5a357ec2a2208a6ab92
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Correct DWARF number for vector registers.

The DWARF numbers of vector registers are already defined in
riscv-elf-psabi. The DWARF number for vector is start from 96.
Correct the DWARF numbers of vector registers.

Differential Revision: https://reviews.llvm.org/D94749