[all-commits] [llvm/llvm-project] bea661: [RISCV] Add intrinsics for RVV 1.0 vrgatherei16

[ShihPo Hung via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bea661d9a52f9abb4fef7cf195092e912c165d34
      https://github.com/llvm/llvm-project/commit/bea661d9a52f9abb4fef7cf195092e912c165d34
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for RVV 1.0 vrgatherei16

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95014


  Commit: 976cf53cc7a5dd03932a6e44b8a9350a05cdaa68
      https://github.com/llvm/llvm-project/commit/976cf53cc7a5dd03932a6e44b8a9350a05cdaa68
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0

Add unordered indexed load: vluxei

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95028


  Commit: 96677503315e689fd3c8f5ef164d8fb9725d4bb3
      https://github.com/llvm/llvm-project/commit/96677503315e689fd3c8f5ef164d8fb9725d4bb3
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
    A llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
    A llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
    A llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D95113


Compare: https://github.com/llvm/llvm-project/compare/bd3ca6666d14...96677503315e