[all-commits] [llvm/llvm-project] b8921a: [RISCV] Update V instructions constraints to confo...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b8921af63b0d746606f2482f3a020ea7cd316cd2
      https://github.com/llvm/llvm-project/commit/b8921af63b0d746606f2482f3a020ea7cd316cd2
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-22 (Fri, 22 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/add.s
    M llvm/test/MC/RISCV/rvv/convert.s
    M llvm/test/MC/RISCV/rvv/invalid.s
    M llvm/test/MC/RISCV/rvv/shift.s
    M llvm/test/MC/RISCV/rvv/sub.s

  Log Message:
  -----------
  [RISCV] Update V instructions constraints to conform to v1.0

Upgrade RISC-V V extension to v1.0-08a0b46.
Update instruction constraints to conform to v1.0.

Differential Revision: https://reviews.llvm.org/D93612