[all-commits] [llvm/llvm-project] 69bc09: [DAGCombiner] Enable SimplifyDemandedBits vector s...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 69bc0990a9181e6eb86228276d2f59435a7fae67
      https://github.com/llvm/llvm-project/commit/69bc0990a9181e6eb86228276d2f59435a7fae67
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/ARM/lowerMUL-newload.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vmulh.ll
    M llvm/test/CodeGen/X86/combine-sra.ll
    M llvm/test/CodeGen/X86/known-signbits-vector.ll
    M llvm/test/CodeGen/X86/min-legal-vector-width.ll
    M llvm/test/CodeGen/X86/uint_to_fp-3.ll
    M llvm/test/CodeGen/X86/vector-trunc.ll

  Log Message:
  -----------
  [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).

Add DemandedElts support inside the TRUNCATE analysis.

REAPPLIED - this was reverted by @hans at rGa51226057fc3 due to an issue with vector shift amount types, which was fixed in rG935bacd3a724 and an additional test case added at rG0ca81b90d19d

Differential Revision: https://reviews.llvm.org/D56387