[all-commits] [llvm/llvm-project] 47228f: [RISCV] Implement vsseg intrinsics.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 47228f785460cdd8f642c42876d394198d6b90c3
      https://github.com/llvm/llvm-project/commit/47228f785460cdd8f642c42876d394198d6b90c3
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Implement vsseg intrinsics.

Define vsseg intrinsics and pseudo instructions. Lower vsseg intrinsics
to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94688


  Commit: e5e329023bb119631e7a756b47598cb0ce9cea5f
      https://github.com/llvm/llvm-project/commit/e5e329023bb119631e7a756b47598cb0ce9cea5f
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Implement vlsseg intrinsics.

Define vlsseg intrinsics and pseudo instructions. Lower vlsseg intrinsics
to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94763


  Commit: a8b96eadfd93f1641c72c378e33af636f463ab02
      https://github.com/llvm/llvm-project/commit/a8b96eadfd93f1641c72c378e33af636f463ab02
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-21 (Thu, 21 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Implement vssseg intrinsics.

Define vlsseg intrinsics and pseudo instructions. Lower vlsseg
intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94863


Compare: https://github.com/llvm/llvm-project/compare/baf6c2987e57...a8b96eadfd93