[all-commits] [llvm/llvm-project] 0f8386: [RISCV] Add addu.w and slliu.w test that uses gete...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f8386c4f6aa804fe43814fcb3ae29d271da82d7
      https://github.com/llvm/llvm-project/commit/0f8386c4f6aa804fe43814fcb3ae29d271da82d7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-20 (Wed, 20 Jan 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.

This is closer to the kind of code that these intrinsics are
targeted at. Note we fail to match slliu.w here because our pattern
looks for (and (shl X, C1), 0xffffffff << C1) rather than
(shl (and X, 0xffffffff), C1). I'll fix this in a follow up
commit.


  Commit: e996f1d4194bccf1c8ca984d695b848c0093bc23
      https://github.com/llvm/llvm-project/commit/e996f1d4194bccf1c8ca984d695b848c0093bc23
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-20 (Wed, 20 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] Add another isel pattern for slliu.w.

Previously we only matched (and (shl X, C1), 0xffffffff << C1)
which matches the InstCombine canonicalization order. But its
possible to see (shl (and X, 0xffffffff), C1) if the pattern
is introduced in SelectionDAG. For example, through expansion of
a GEP.


Compare: https://github.com/llvm/llvm-project/compare/735a07f04785...e996f1d4194b