[all-commits] [llvm/llvm-project] 8ca4b1: [RISCV] Implement vlseg intrinsics.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ca4b174d703e8676c6d47a2e25895c82e2e2ab7
      https://github.com/llvm/llvm-project/commit/8ca4b174d703e8676c6d47a2e25895c82e2e2ab7
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-20 (Wed, 20 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    A llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Implement vlseg intrinsics.

For Zvlsseg, we need continuous vector registers for the values. We need
to define new register classes for the different combinations of (number
of fields and LMUL). For example,

when the number of fields(NF) = 3, LMUL = 2, the values will be assigned
to (V0M2, V2M2, V4M2), (V2M2, V4M2, V6M2), (V4M2, V6M2, V8M2), ...

We define the vlseg intrinsics with multiple outputs. There is no way to
describe the codegen patterns with multiple outputs in the tablegen
files. We do the codegen in RISCVISelDAGToDAG and use EXTRACT_SUBREG to
extract the values of output.

The multiple scalable vector values will be put into a struct. This
patch is depended on the support for scalable vector struct.

Differential Revision: https://reviews.llvm.org/D94229