[all-commits] [llvm/llvm-project] ce8b39: [RISCV] Add DAG combine to turn (setcc X, 1, setne...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ce8b3937ddad39536e6e715813682d9198229fb5
      https://github.com/llvm/llvm-project/commit/ce8b3937ddad39536e6e715813682d9198229fb5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-19 (Tue, 19 Jan 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/select-and.ll
    M llvm/test/CodeGen/RISCV/select-or.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.

If we are able to compare with 0 instead of 1, we might be able
to fold the setcc into a beqz/bnez.

Often these setccs start life as an xor that gets converted to
a setcc by DAG combiner's rebuildSetcc. I looked into a detecting
(xor X, 1) and converting to (seteq X, 0) based on boolean contents
being 0/1 in rebuildSetcc instead of using computeKnownBits. It was
very perturbing to AMDGPU tests which I didn't look closely at.
It had a few changes on a couple other targets, but didn't seem
to be much if any improvement.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94730