[all-commits] [llvm/llvm-project] 5626ad: [X86][SSE] combineVectorSignBitsTruncation - fold ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406
      https://github.com/llvm/llvm-project/commit/5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-01-19 (Tue, 19 Jan 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-trunc.ll

  Log Message:
  -----------
  [X86][SSE] combineVectorSignBitsTruncation - fold trunc(srl(x,c)) -> packss(sra(x,c))

If a srl doesn't introduce any sign bits into the truncated result, then replace with a sra to let us use a PACKSS truncation - fixes a regression noticed in D56387 on pre-SSE41 targets that don't have PACKUSDW.